A Test Environment for Validation of Subthreshold and Leakage Current Estimation Method in CMOS Logic Gates

Several analytical methods for estimating the subthreshold and gate oxide leakage currents in CMOS circuits have been presented in the literature. However, such currents are strongly dependent on the fabrication process targeted, and the methods present different prediction data accuracy according to the profile of logic gates, in terms of transistor arrangements, stacked devices, and gate sizing. In this work is presented a test environment developed to evaluate and validate the method of subthreshold and gate leakage current estimation for general CMOS logic gates proposed in [1]. PTM 32 nm CMOS parameters were considered to demonstrate the proposed test environment.